RISC-V CPU Development

Track our journey in developing next-generation RISC-V processors

Development Roadmap

Q2 2023

Architecture Design

Completed initial RISC-V processor architecture design with custom extensions for enterprise workloads.

ISA Definition Complete Microarchitecture Specification Performance Modeling
Q4 2023

RTL Implementation

Completed RTL design and verification of the core processor units including ALU, FPU, and cache controllers.

Core RTL Complete Cache Hierarchy Memory Controller
Q2 2024

FPGA Prototype

Successfully implemented and tested processor design on FPGA platforms, validating functionality and performance.

FPGA Implementation Linux Boot Success Benchmark Validation
Q4 2024

Silicon Tapeout

Currently in the final stages of silicon design and preparing for first tapeout using 7nm manufacturing process.

Physical Design 95% DRC/LVS Verification Timing Closure
Q2 2025

Silicon Validation

Receive first silicon samples and conduct comprehensive validation and characterization testing.

Silicon Samples Functional Testing Performance Validation
Q4 2025

Production Release

Begin mass production and integration into Ternic server products for customer delivery.

Mass Production Server Integration Customer Delivery

Technical Milestones

Core Architecture

100%
64-bit RISC-V ISA implementation
Custom extensions for enterprise features
Out-of-order execution pipeline

Memory Subsystem

100%
Multi-level cache hierarchy
DDR5 memory controller
Advanced prefetching algorithms

I/O and Interconnect

95%
PCIe 5.0 controller
High-speed network interfaces
Interconnect fabric optimization

Security Features

90%
Hardware root of trust
Memory protection units
Cryptographic accelerators

Physical Design

95%
7nm process optimization
Power delivery network
Final timing closure

Software Stack

85%
Linux kernel support
Compiler optimizations
Performance tuning

Performance Projections

Single-Core Performance

Ternic RISC-V
2,850 pts
Intel Xeon
2,550 pts
AMD EPYC
2,700 pts

SPEC CPU2017 Integer benchmark scores (projected)

Power Efficiency

Ternic RISC-V
125 pts/W
Intel Xeon
88 pts/W
AMD EPYC
100 pts/W

Performance per watt comparison (projected)

Memory Bandwidth

Ternic RISC-V
450 GB/s
Intel Xeon
380 GB/s
AMD EPYC
400 GB/s

Peak memory bandwidth (projected)

Our Development Team

52 Engineers
28 PhDs
200+ Years Combined Experience
45 Patents Filed

Areas of Expertise

Processor Architecture RISC-V ISA VLSI Design Memory Systems Cache Design Physical Design Verification Performance Modeling Security Architecture Compiler Development